1. Field of the Invention
The present invention relates in general to digital computer systems, and more particularly to cache memory systems.
2. Description of the Prior Art
Cache memories are used in many computer systems to improve system performance. A cache memory is a relatively small, fast memory which resides between a central processor and main system memory. Whenever the processor reads the contents of a memory location which is stored in the cache memory, the time required to access such location is drastically reduced. A good cache technique can provide a "hit ratio" of well over ninety percent, meaning that no main memory access is necessary for over ninety percent of the read operations performed. Access of data which is stored in the cache can improve access times by factors of three to ten times.
A cache performs functions requiring two different types of memory. The first type is the data memory, in which the data is actually stored. The second type is known as a tag memory, or tag RAM, which is used to determine which memory locations are actually stored in the cache. In general, the cache tag RAM contains a plurality of entries corresponding to the entries of the data cache. Each entry is indexed by some number of least significant bits of the address generated by the central processor, with the tag entry itself containing the most significant bits of the memory location which is stored in the corresponding data cache entry. If the most significant bits stored in the cache tag match the most significant bits of the address currently being generated, with the least significant bits of this address acting as an index to the tag RAM, a cache "hit" has occurred and the data to be read may be taken from the corresponding data cache entry. If data corresponding to the desired address is not located in the data cache, the tag entry will not match the most significant bits of the address, and a "miss" occurs. This indicates that the data must be retrieved from main system memory and placed into the data cache. At this time, the current contents of the cache tag entry are overwritten with the most significant bits of the newly retrieved address.
Cache tag RAMs are typically wired-NOR'ed together to increase the effective width of the resulting cache tag RAM. As a result, the address space of the cache tag RAM may be expanded.
FIG. 1 illustrates an example of two tag RAMs wired together in a wired-NOR configuration. Tag RAM 2 has a number of input pins 4 for least significant bits of an address and a number of input pins 6 for the most significant bits of an address. Depending on the signals sent to input pins 4 and 6, tag RAM 2 may change output at output pin 8 in response to the input. Similarly, tag RAM 10 includes input pins 4 and 6 and output pin 8. Output pin 8 of tag RAM 2 controls the gate of transistor Q1 while output 8 of tag Ram 10 controls the gate of transistor Q2. These two transistors control the output at output pin, MATCH. A resistor R has one end connected to the source/drains of transistors Q1 and Q2 and has another end connected to power supply voltage VCC. Additionally, transistors Q1 and Q2 have their source/drains connected to the bus capacitance C, which is also connected to power supply voltage VSS. Typically, power supply voltage VCC is at a higher voltage than power supply voltage VSS.
This match bus configuration is well known in the prior art. The performance of the pull-up resistor R in pulling output pin MATCH high is not as fast as desired because of the RC time constant. Resistor R also can cause an increase in pull-down time because the open drain transistors must overcome resistor R to pull down the signal at output MATCH. If resistor R is large, pull-down time is decreased, but pull-up time is increased.
It would be desirable to improve the output transition time of the output at output pin MATCH or any other wired-NOR type of signal. Therefore, it would be desirable to have a method and apparatus for reducing the effects of RC time constants on pull-up and pull-down time of an output to a wired-NOR system.